The Hybrid Memory Cube
Frequently Asked Questions
Notes to User: This is a living and informal document. We encourage you to comment, ask additional questions, and make suggestions below. If you have comments you would like to ask privately, please contact us at HPC@micron.com with the subject: ATTN: HMC FAQ Zendesk
I. Introduction: Basics of the HMC
What is the architecture?
An HMC consists of a single package containing multiple memory die and one logic die, stacked together using through-silicon via technology. Within an HMC, memory is organized into vaults. Each vault is functionally and operationally independent. Each vault has a memory controller (called vault controller) in the logic base that manages all memory reference operations within that vault. Each vault controller determines its own timing requirements.
The basic internals of data movement is below:
In a nutshell, why should I use the HMC?
Past Generation of DRAM have been simple “dumb” devices that contain almost no logic and share a common data bus. In these devices, the performance of the main memory system as a whole is directly proportion to the performance of the memory devices connected to the data bus. However, the HMC introduces extra parallelism which makes the performance of any individual device less critical. That is, many memory banks and many memory controllers decrease the likelihood of bank conflicts and allow many requests to be in-flight at any given time. Having many in progress requests takes any individual device off the critical path and allows high throughput to be maintained even when memory devices are slower.
What are some workloads that would potentially utilize the HMC and why?
Any application that requires high bandwidth, memory parallelism, and high random access (i.e. Molecular Dynamics, Big Data (Map Reduce), Graph Problems, etc.) has the potential to work well on an HMC. More information coming.
Can you give me some example comparisons of using DDR versus HMC for different types of workloads?
To be Determined