Release Notes

Supported Boards

  • SB801: 1 x 10G full-width link per FPGA, controller core running at 250 MHz
  • AC510: 2 x 15G half-width links per FPGA, controller core running at 187.5 MHz
    • 2 HMC links with one HMC controller per link


  • This release has increased bandwidth performance on HMC write requests
  • This release uses the Micron HMC BFM version hmc_bfm_gen2_r31047 for simulation
  • The BFM must be obtained from the support page, sign up for an account and request the BFM
  • low-level PHY with
    • link training
    • scrambling and descrambling
    • lane bonding (this is different in the 15G versus 10G versions of the PHY)
  • high-level controller with
    • token-based flow control for FPGA -> HMC direction
    • open-loop response mode for HMC -> FPGA direction
    • CRC detection
    • both TX and RX retry logic
    • arbitration for 5 user ports per controller
    • user-specified clock for the interface on each user port
  • GUPS sample
    • integrated into the same flow as the rest of the Pico Framework samples
  • software reads / writes the memory
    • Enable users to write / read the HMC from software using WriteRam() / ReadRam () software calls
    • we currently steal 1 controller user port per HMC controller to enable this feature
      • therefore SB800 only has 4 usable user ports per FPGA, AC510 has 9 usable user ports per FPGA
    • calls to WriteRam() and ReadRam() can be up to 1 GB per call
    • Data reordering is performed in the FPGA for ReadRam() so HMC response data is in order
  • software bringup of the HMC
    • brings up the HMC on the first software call to WriteRam / ReadRam
    • we steal a section of the User PicoBus address space to talk to the HMC controller, so User Modules are restricted to only using PicoBus addresses 0x10000 to 0xF0000
  • User Guide
    • This is currently included in the tarball for the HMC release in the ./doc directory


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